MG80C286-10/883

MG80C286-10/883

Shenzhen, China
Shenzhen, China
Beginner
86-755-83982456
Qrainy Xu
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Basic Information

Model Number MG80C286-10/883
Features • This Circuit is Processed in Accordance to MIL-STD- 883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Compatible with NMOS 80286/883 • Static CMOS Design for Low Power Operation - ICCSB = 5mA Maximum - ICCOP = 185mA Maximum (80C286-10/883) - ICCOP = 220mA Maximum (80C286-12/883) • Large Address Space - 16 Megabytes Physical - 1 Gigabyte Virtual per Task • Integrated Memory Management, Four-Level Memory Protection and Support for Virtual Memory and Operating Systems • Two 80C86 Upward Compatible Operating Modes - 80C286/883 Real Address Mode - Protected Virtual Address Mode • Compatible with 80287 Numeric Data Co-Processor Description The Intersil 80C286/883 is a static CMOS version of the NMOS 80286 microprocessor. The 80C286/883 is an advanced, high-performance microprocessor with specially optimized capabilities for multiple user and multi-tasking systems. The 80C286/883 has built-in memory protection that supports operating system and task isolation as well as program and data privacy within tasks. The 80C286/883 includes memory management capabilities that map 230 (one gigabyte) of virtual address space per task into 224 bytes (16 megabytes) of physical memory. The 80C286/883 is upwardly compatible with 80C86 and 80C88 software (the 80C286/883 instruction set is a superset of the 80C86/80C88 instruction set). Using the 80C286/ 883 real address mode, the 80C286/883 is object code compatible with existing 80C86 and 80C88 software. In protected virtual address mode, the 80C286/883 is source code compatible with 80C86 and 80C88 software but may require upgrading to use virtual address as supported by the 80C286/883’s integrated memory management and protection mechanism. Both modes operate at full 80C286/883 performance and execute a superset of the 80C86 and 80C88 instructions. The 80C286/883 provides special operations to support the efficient implementation and execution of operating systems. For example, one instruction can end execution of one task, save its state, switch to a new task, load its state, and start execution of the new task. The segment-not-present exception and restartable instructions.

Delivery terms and packaging

Port: HONGKONG

Payment term

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    Дата события:

    12.10.2016 - 18.10.2016
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